Insider Brief
- SEALSQ Corp announced a strategic shift toward CMOS-compatible quantum computing architectures, prioritizing silicon spin qubits and electrons-on-helium platforms to align scalability with established semiconductor manufacturing.
- The company highlighted silicon-based approaches and FDSOI as potential enablers for integrating quantum processors with classical CMOS control electronics while managing noise and power constraints.
- SEALSQ is embedding post-quantum cryptography and hardware-based trust mechanisms into its silicon roadmap to secure quantum control systems, firmware, and distributed infrastructure.
PRESS RELEASE — SEALSQ Corp (NASDAQ: LAES) (“SEALSQ” or “Company”), a company that focuses on developing and selling Semiconductors, PKI, and Post-Quantum technology hardware and software products, today announced an increased technology-driven focus on semiconductor CMOS-compatible quantum computing architectures. This strategic emphasis reflects SEALSQ’s conviction that long-term quantum scalability will be achieved through deep alignment with semiconductor technology. By prioritizing silicon spin qubits and electrons-on-helium platforms, SEALSQ is concentrating its investments on qubit technologies that can be fabricated, integrated, and scaled using established semiconductor CMOS processes and manufacturing capabilities.
Both silicon spin qubits and electrons-on-helium platforms approaches are promising for semiconductor CMOS-compatible quantum computing: silicon spin qubits use electrons in silicon and can be made with chip-making methods similar to CMOS, which may help with scaling and manufacturing, while electrons-on-helium qubits use electrons above superfluid helium on a silicon chip and can use CMOS-compatible controls, offering a low-noise alternative approach.
CMOS compatibility is not just a technology or manufacturing preference; it is a system-level enabler. Quantum processors require dense arrays of control electrodes, high-speed signal routing, cryogenic-compatible electronics, and precise calibration and monitoring infrastructure. Silicon-based quantum platforms offer a credible path to the co-design and eventual co-integration of quantum devices with classical CMOS control circuitry. In this context, FDSOI appears to be a strong compromise for achieving acceptable noise and power consumption levels. FDSOI is a wafer-level semiconductor technology that uses a thin silicon layer on an insulating layer to reduce power consumption and noise.
Carlos Moreira, Founder and CEO of SEALSQ, commented: “From our perspective, this technology alignment is a real advantage over other quantum approaches, such as superconducting or ion-trap systems. While those platforms are scientifically impressive, they often depend on specialized materials, custom fabrication steps, or complex optical and vacuum setups that do not align as naturally with mainstream semiconductor manufacturing. In contrast, silicon spin qubits and electrons-on-helium architectures are designed from the start to evolve within the semiconductor ecosystem. This alignment not only accelerates learning cycles but also ensures a smooth transition from research to production. Most importantly, it allows us to enable security-by-design through post-quantum cryptography (PQC) and hardware-based trust, positioning SEALSQ at the intersection of quantum innovation and secure manufacturing.”
At the same time, alongside its work on CMOS-compatible quantum hardware, SEALSQ recognizes that quantum computers must rely on strong security systems and is therefore integrating post-quantum cryptography (PQC) and hardware-based trust mechanisms directly into the system architecture. As quantum processors advance toward large-scale, silicon-manufactured platforms, security becomes a foundational architectural requirement, not an afterthought.
Post-quantum cryptography (PQC) plays a foundational role in this architecture. As quantum computing advances and increases the risk to classical public-key cryptography, SEALSQ is integrating PQC algorithms and hardware-based trust mechanisms in secure silicon to help ensure that quantum control systems, firmware updates, calibration data, and interconnect communications remain resilient against both classical and quantum-enabled attacks. This is especially critical in distributed quantum systems, where control electronics, cryogenic interfaces, and cloud-connected orchestration layers must exchange sensitive data securely. Securing these platforms involves implementing strong authentication mechanisms; it can also be used to secure FPGA configurations when manipulating qubits (e.g., error treatment algorithms).
Secure elements fabricated alongside or integrated with quantum control circuitry allow for trusted boot, device attestation, and secure key storage, ensuring that only authenticated software and authorized operators can access or modify quantum systems. This capability is essential as quantum computers transition from isolated laboratory instruments to networked, mission-critical infrastructure.
By combining CMOS-based quantum architectures with embedded post-quantum security, SEALSQ is addressing a fundamental challenge of the quantum era: ensuring that the machines designed to break today’s cryptography are themselves secure, trustworthy, and sovereign by design. This convergence of quantum physics, semiconductor engineering, and cryptographic resilience positions silicon-based quantum computing as not only scalable, but also secure enough for real-world deployment in government, industrial, and critical infrastructure environments.
