Insider Brief
- D-Wave has published research in Nature demonstrating a two-qubit entangling gate for its dual-rail erasure qubit architecture aimed at improving quantum error correction efficiency.
- The company reported approximately 99.9% fidelity for two-qubit operations with gate times of about 500 nanoseconds while maintaining native hardware-level error detection.
- The research supports D-Wave’s gate-model roadmap focused on reducing hardware overhead requirements for fault-tolerant quantum computing systems.
Press release – D-Wave Quantum Inc. (Nasdaq: QBTS), (“D-Wave” or the “Company”), the only dual-platform quantum computing company providing both annealing and gate-model systems, software, and services, today announced a major research breakthrough advancing the path to practical, fault-tolerant gate-model quantum computing. Published in the peer-reviewed scientific journal Nature, the research demonstrates a fast, high-fidelity, two-qubit entangling gate that preserves the error-correction advantages of D-Wave’s superconducting dual-rail qubit architecture. The results address one of the industry’s most consequential challenges by reducing the immense quantum and classical hardware overhead typically required to detect and correct quantum errors as systems scale.
The paper, “An entangling gate for dual-rail erasure qubits,” details a new two-qubit entangling gate, a fundamental building block of quantum computation, designed to support efficient quantum error correction. The research demonstrates approximately 99.9% fidelity during two-qubit operations, with fast gate times of about 500 nanoseconds, enabled by native hardware-level error detection. Leveraging these results, D-Wave simulations indicate its dual-rail architecture could reduce the logical error rate by as much as a factor of 10 for each increment in error correction, significantly reducing the physical qubit overhead required for fault-tolerant quantum computing.
“Gate-model quantum computing’s greatest remaining challenge is not simply building more qubits. It is building systems that can correct errors efficiently as they scale,” said Dr. Alan Baratz, CEO of D-Wave. “Superconducting quantum computers are known for speed, but achieving the high fidelity needed for scalable, fault-tolerant systems has remained a challenge. This research demonstrates that our dual-rail architecture combines fast superconducting operations with high-fidelity performance while preserving native hardware-level error detection. We believe that this work confirms our path to commercial fault-tolerant quantum computing is practical and achievable.”
Removing a Major Barrier to Fault-Tolerant Quantum Computing
Quantum information is inherently fragile and highly susceptible to errors, making efficient quantum error correction essential for the development of reliable, fault-tolerant gate-model quantum computers. In many gate-model architectures, correcting those errors requires large numbers of additional physical qubits and operations, creating substantial engineering complexity, cost, and performance constraints. D-Wave’s dual-rail architecture is designed to create a favorable error hierarchy in which the most common quantum errors are also the easiest to correct. The newly published research demonstrates that this favorable error hierarchy is preserved during two-qubit operations, with the technology maintaining both speed and high fidelity. The results establish an important foundation for scalable quantum error correction with substantially lower hardware overhead.
“The entangling gate demonstrated through this research is already integrated into our gate-model systems, where it is delivering comparable performance,” said Dr. Robert Schoelkopf, chief scientist at D-Wave. “We believe these results provide strong evidence that the core architectural principles underpinning our gate-model development roadmap can deliver the speed, fidelity and error-correction efficiency required for practical, fault-tolerant quantum computing.”
The research supports D-Wave’s recently announced gate-model development roadmap, which targets a 2032 completion of a 100-logical-qubit system capable of successfully performing more than 1 million operations. The roadmap brings together D-Wave’s superconducting dual-rail architecture and integrated cryogenic control technology to enable more efficient error detection and awareness as systems scale. D-Wave’s roadmap is targeting an error reduction rate, or Lambda, of 10. Lambda is a measure of how rapidly a quantum computer’s errors are reduced as more error-correction capability is added. A Lambda of 10 means the system becomes 10 times more reliable with each increment in error correction, making it possible to achieve low logical error rates required for fault-tolerant quantum computing with far fewer physical qubits.
“Building a fault-tolerant quantum computer requires systematically solving a series of difficult scientific and engineering challenges, with each success bringing us closer to a scalable system,” said Dr. Trevor Lanting, chief development officer at D-Wave. “This research demonstrates one of the foundational capabilities of our dual-rail architecture and brings us an important step closer to fault-tolerant gate-model quantum computing.”
The research further advances D-Wave’s dual-platform strategy of developing complementary annealing and gate-model quantum computing technologies to address the full range of computationally complex problems.
Read the paper, “An entangling gate for dual-rail erasure qubits,” in Nature here.
Learn more about D-Wave’s gate-model quantum computing here.
