Insider Brief
- Classiq and ParityQC announced a partnership to combine quantum software optimization and hardware-aware architecture techniques for more efficient quantum program execution.
- The collaboration will integrate Classiq’s quantum software engineering platform with ParityQC’s Parity Twine technology to reduce circuit complexity and improve execution on quantum hardware with limited connectivity.
- The companies aim to support scalable quantum software development across current noisy quantum devices and future fault-tolerant quantum systems.
Press release – The quantum software company Classiq and the quantum architecture company ParityQC announced a partnership to integrate ParityQC’s Parity Twine technology with Classiq’s quantum software engineering platform, giving developers and enterprises a more efficient path from quantum algorithm design to execution on quantum hardware.
The collaboration focuses on a key opportunity in quantum computing: translating high-level quantum computing applications into circuits that run efficiently on quantum hardware with limited qubit connectivity. Classiq’s universal optimization protocol and ParityQC’s algorithm-aware techniques are leading, and complementary, innovative optimization techniques that will be combined into an integrated methodology. The companies aim to reduce circuit complexity and costly SWAP operations, a common bottleneck in executing quantum programs on today’s quantum computers.
This Germany-Israel cross-border initiative will focus on scalable quantum software infrastructure for current noisy quantum devices as well as future fault-tolerant quantum systems. The joint work is designed to enable developers to move from Classiq’s high-level software engineering platform to highly optimized hardware execution, by leveraging both companies’ technologies. The collaboration will strengthen hardware-agnostic approaches that enable interoperability across multiple quantum platforms, critical as quantum hardware continues to evolve rapidly.
“Quantum computing will only become practical at scale if the software layer can automatically bridge the gap between algorithmic intent and the constraints of real machines,” said Nir Minerbi, co-founder and CEO of Classiq. “By working with ParityQC, we are combining high-level quantum software automation with hardware-aware architecture innovation so that developers can build, optimize and execute quantum applications more efficiently across the evolving hardware ecosystem.”
ParityQC’s Parity Twine technology is designed to address routing and connectivity challenges by improving how quantum information is represented, distributed, and interpreted across hardware layouts. The combination of Parity Twine running on an IBM Quantum Heron processor showed a new world-record benchmark implementation for QFT, nearly doubling the previous benchmark. Integrated with Classiq’s model-first platform, the approach is expected to help quantum teams generate more efficient quantum programs while preserving portability across different quantum computing systems.
“Integrating the Parity Tools with Classiq‘s platform brings hardware-aware compilation directly into high-level development workflows, lowering the barrier to create useful quantum applications,” said Wolfgang Lechner, Co-CEO of ParityQC.
“Meaningful progress in quantum computing is built on collaboration, and bringing our complementary strengths together is what moves the whole field forward,” added Magdalena Hauser, Co-CEO of ParityQC.
The companies confirmed the collaboration is intended to support long-term ecosystem development beyond technology integration. Areas of focus may include academic research, workforce development, benchmarking methods and future standards for quantum software infrastructure.
As enterprises and governments increase investment in quantum computing, scalable architecture and software tools are expected to serve as the missing link between quantum computing’s theoretical promise and its deployable reality.
The collaboration is aimed at accelerating that transition by combining automation, portability and hardware-aware optimization in a single development path.
