- Last Modified: July 27, 2022

**Inside Classiq’s Synthesis Engine**

** **At a quick glance, Classiq’s Quantum Algorithm Design (QAD) platform looks like a relatively-quick way to build unfathomably large quantum circuits. As any quantum algorithm designer surely knows, manually designing circuits can be quite challenging even when using just a few qubits. Designing a circuit for a 1,000-qubit quantum computer will be virtually impossible; you can’t even view any significant percentage of the circuit on a single computer screen. But, it turns out, designing large quantum circuits is only the tip of Classiq’s proverbial iceberg.

The impetus for the platform is apparently something Classiq calls “functional level optimization.” This revelation came from a throwaway line by Chief Marketing Officer Yuval Boger during a presentation titled “__Optimized and Hardware Aware Solutions to Quantum Problems__” to the Washington DC Quantum Computing Meetup. He was joined by Dr. Erik Garcell, Product Marketing Manager.

To explain what Classiq means by “functional level optimization,” a little background on quantum circuit optimization might be helpful. In the interest of full disclosure, the background that follows borrows heavily from the presentation, because it builds up to the insightful moment.

**What is quantum circuit optimization and why is it important?**

Today’s Noisy Intermediate-Scale Quantum (NISQ) computers have limited numbers of qubits, greatly constraining the size of the problems that can be addressed. Those limited numbers of qubits also have limited connectivity, which means that quantum information needs to be moved around in order to perform many operations. That transfer of quantum information is quite error-prone, which makes the results of these operations essentially useless. Furthermore, these qubits have limited coherence, which means that quantum information is lost quickly. Consequently, there is a race against time to perform computation before quantum information is lost naturally.

According to Yuval, Classiq looks to Apollo 11’s on board computer for inspiration; after all, NASA sent humans to the moon and back using only 72 kilobytes of ROM. Similarly, the solution to NISQ limitations is to take a given problem and compress it so that it requires fewer resources. Reducing the number of qubits you need, for example, allows bigger problems to be solved on existing quantum computers than would otherwise be the case. Furthermore, designing shorter, shallower circuits yields better results, potentially even useful results. Imagine if you could do both!

The significance of this during the NISQ era cannot be overstated. The results of quantum computation are usually noise, from which correct solutions cannot be extracted. The ability to optimize circuits and perform practical quantum computation before others potentially realizes a competitive advantage.

**What does Classiq mean by “hardware-aware” circuits?**

As Yuval put it, “hardware-aware circuits are circuits that understand the hardware that they run on.”

In other words, different quantum computers have different characteristics. A hardware-aware circuit recognizes, for example, that a higher number of qubits are available. This might allow for a shallower circuit, which might contribute toward winning the race against time (decoherence). A hardware-aware circuit also recognizes greater qubit connectivity. This might allow qubits to be assigned in such a way as to reduce the aforementioned error-prone movement of quantum information.

Those two optimizations are universal across gate-based quantum computers, but hardware-aware circuits also recognize and take advantage of features that not all quantum computers have. For example, mid-circuit measurements are a way to extract classical information from a circuit before it has time to become lost to the environment. Also, different native gate sets may allow individual operations to be executed in fewer steps. For example, a native Toffoli gate is noticeably faster and more efficient a standard Toffoli gate, which is composed of a modest number of error-producing multi-qubit operations. Furthermore, all quantum computers have different noise models. Individual qubits and connections are noisier (more error-prone) than other qubits and connections, and a hardware-aware circuit seeks to utilize the highest-quality configuration.

The limitations of the Classiq synthesis engine, therefore, would seem to be the limitations of the hardware available to you. But, more on that later….

**What is “Gate Level Optimization?”**

Gate level optimization refers to making the quantum assembly language (QASM) of a circuit more efficient. This is typically done by transpilers, for example Quantinuum’s t|ket and Qiskit’s Pass Manager. This may include reassigning qubits to reduce the number of SWAPs that are required. SWAP gates are the aforementioned error-prone method for moving quantum information around. Reassignment means that a circuit designed to have specific operations executed on the first virtual qubit, for example, might actually be executed on the third physical qubit because it’s more efficient to do so; such optimization could be completely hidden from algorithm designers, as the third physical qubit would be measured as the first virtual qubit, as the circuit was designed.

An example of gate based optimization can be as simple as two sequential Hadamard gates. There is no need to execute two Hadamards in a row, because they cancel each other out. Therefore, these two operations can be safely removed from the circuit. The performance improvement is even more pronounced when multi-qubit operations are removed. And, again, removing unnecessary circuit depth may allow algorithms to be run on smaller quantum computers as long as the reduction in the number of qubits still allows for a circuit depth that does not exceed the maximum coherence time of those qubits.

The limitation of gate level optimization, according to Yuval, is that it misses the “big picture.” Here’s where functional level optimization comes in.

**What is “Functional Level Optimization?”**

Functional level optimization is more practical than gate level optimization, allowing circuit designers to specify hardware constraints such as maximum circuit width and maximum circuit depth. There is little point in designing a 20-qubit circuit, for example, if neither 20 real qubits are available to the user nor a classical simulator can finish processing it before generating runtime errors. Therefore, the real impetus behind Classiq’s platform is not just generating large quantum circuits, but generating large quantum circuits that can actually run on hardware that is available to the user.

The functional model of quantum circuit design also involves specifying parameters for functional blocks. For example, a state preparation block may specify the number of qubits to use and the probabilities to encode. Zero consideration is given to the operations that must be executed to implement this. It’s worth noting that users can create their own functional models, otherwise users merely specify what they want without concern as to how it is done.

The value of this can be seen, for example, if you take a random circuit and include an adder somewhere in the algorithm. Which is more efficient for that particular circuit, a QFT adder or a ripple adder? It doesn’t matter! The end result is the same, so high-level optimization simply takes into consideration the functionality that the user wants, and then uses the optimal subroutine. Hence the name “functional level optimization;” all that matters is the desired functionality; what is the absolute best way to implement it?

It’s worth noting that lower level optimization will follow, of course. Gate level optimization will follow. But, high-level, functional level optimization opens up more opportunities to generate the least wide, least deep circuits to optimize at the gate level.

For other examples, high-level optimization considers how many auxiliary qubits to use depending on how many are available and how the different configurations will affect circuit depth and the number of multi-qubit operations. Also, qubits that will not be reused do not need to be uncomputed. And, maybe the order of certain operations can be changed to improve efficiency.

One trick that was highlighted during the recent #ClassiqCodingCompetition, the intent of which was to raise awareness of quantum circuit optimization, was how accuracy can be sacrificed to reduce circuit depth. Some algorithms achieve greater accuracy by adding circuit depth, but the converse is also true. If less accuracy is required, circuit depth can be sacrificed. Unlike during the competition, however, this can be done automatically instead of manually. One of the parameters of the Classiq synthesis engine is the error rate; simply set the desired value, generate the circuit, and run it. It can’t get much simpler than that. Note that a PhD is not required to type a number; another one of Classiq’s goals is to lower the barriers to entry to use quantum computing.

Classiq’s secret seems a bit brute force, and yet it takes mere seconds to run. Classiq’s engine purportedly generates millions of circuits and selects the best one. Not only is that impossible for humans to do, other transpilers don’t do that; you get one circuit. If you are so inclined, you can transpile a circuit many times and select the best result, but you’re not realistically going to re-generate and re-transpile the circuit millions of times until you can have a high degree of confidence that you have the absolute best circuit you can get. But, that’s what QAD was designed to do. And, on top of that, you can update a parameter, tap a button, and do it all over again in mere seconds.

In short, a user selects a high-level model and defines the constraints. Classiq’s library is full of shortcuts, this time intended to reduce barriers to entry to users with different educational backgrounds (physics, finance, etc.). The Classiq synthesis engine then generates code for the user-selected leading open source library (Qiskit, Cirq, etc.), or it can generate OpenQASM. The resultant code can then be transpiled for any universal gate-based quantum computer backend. So, again, the real impetus behind Classiq’s synthesis engine is not just generating massive circuits for the sake of it, rather it is generating optimized circuits for the hardware available to the user, whether that user has 5 poorly-connected noisy qubits or 1,000 well-connected fault-tolerant qubits.

**Why is Functional Level Optimization Significant?**

Consider a very simple example, starting with using the free IBM Quantum backends. Imagine you design a circuit for the 7-qubit ibm_oslo, but the queue is very long. Maybe the device is even offline for routine maintenance. The problem is that ibm_oslo is the only free 7-qubit device. To run the circuit now, you would have to completely redesign it to use one of the free 5-qubit devices. That could be time-consuming, to put it modestly. The purpose of Classiq’s QAD platform is less about building impossibly large circuits, although it does that, and it’s more about taking the 7-qubit circuit you’ve got, adjusting precisely one parameter, and generating a 5-qubit circuit with the exact same functionality as the 7-qubit circuit within seconds.

Now imagine you’ve been granted access to the IBM Quantum Researchers program. Now you have access to the 16-qubit ibmq_guadalupe, and maybe you can use those extra qubits to reduce circuit depth enough to generate meaningful results. You have the option to spend a few hours, or more, redesigning the circuit from scratch, or a few seconds updating that same one parameter again. You choose the latter, of course.

Now imagine you’ve opted to pay-as-you-go for one of IBM Quantum’s 27-qubit devices. You buy a larger monitor so you can actually see all of the circuit, and then you painstakingly redesign the circuit yet again, gate by gate, for hours on end.

No, of course you don’t. You update that parameter again, queue up the circuit, and go get a cup of coffee.

The important thing is that, as the name “functional level optimization” suggests, the functionality of all these circuits is precisely the same. The functional blocks are specified one time. The logical flow between them is specified one time. But, you’ve run the algorithm on a Rigetti superconducting qubit device and now you want to run it on a Honeywell ion trap device with a different qubit count, and it’s as easy as updating a couple of parameters.

One interesting question during the presentation was not about the hardware available, but the cost of it. It is possible to set the functional model parameters to optimize the cost of fee-based quantum computing. Therefore, the limits of the Classiq synthesis engine are not really the limits of the hardware available to you, but rather the limits of the Classiq synthesis engine are the limits of the hardware that you give to it.

**Conclusion**

I once tested Classiq’s marketing claim that it can generate 1,000-qubit circuits. It was a trivial circuit, but, sure enough, all 1,000 qubits were there. It’s worth noting that IBM Quantum choked on the OpenQASM, but I verified Classiq’s claim nonetheless.

At the time, I thought that was sufficient. I wouldn’t want to manually design a 1,000-qubit circuit.

But, Yuval’s throwaway line about exploring millions of circuits was a real eye-opener. It reminded me of Java’s old “write once, run anywhere” slogan, in the sense that you can define your functional blocks once, and define their logical flow once, and then just keep generating new circuits for different-sized quantum computers at different providers with different qubit technologies. So, it’s not an exact analogy, but from a certain point-of-view Classiq’s synthesis engine is a quantum Java Virtual Machine.

Ironically, despite quantum computing’s reputation as being challenging, programming in Java is actually harder than using Classiq’s QAD platform.