Insider Brief
- SEALSQ Corp and Lattice Semiconductor announced a collaboration to integrate TPM-based post-quantum security into select Lattice FPGA platforms.
- A proof-of-concept combines Lattice secure FPGAs with SEALSQ’s QS7001 and QVault TPM secure root-of-trust technologies to demonstrate embedded post-quantum cryptography at the hardware level.
- The joint solution targets mission-critical edge and embedded applications and will be demonstrated at Embedded World 2026.
PRESS RELEASE — SEALSQ Corp (NASDAQ: LAES) (“SEALSQ” or “Company”), a company that focuses on developing and selling Semiconductors, PKI, and Post-Quantum technology hardware and software products, today announced its collaboration with Lattice Semiconductor (NASDAQ: LSCC) to integrate TPM-based advanced post-quantum security capabilities into select Lattice FPGA solutions. This collaboration addresses the rapidly growing need for quantum-resistant technologies in mission-critical applications for edge computing and other high-stakes environments.
“This collaboration perfectly illustrates SEALSQ’s strategy of extending our leadership in post-quantum security beyond direct OEM sales,” said Bernard Vian, General Manager of SEALSQ. “We continue to deliver ready-to-deploy and custom secure chips directly to customers, while also leveraging our deep expertise in post-quantum hardware and flexible semiconductor design capabilities to empower strategic partners across the industry. Collaborating with Lattice allows us to bring our cutting-edge, tailored PQC protection to their FPGA platforms, accelerating the secure transition to quantum-resistant systems for a broad range of high-performance applications.”
“Lattice is committed to advancing security for our customers as the industry prepares for a post-quantum future. By combining SEALSQ’s QS7001 and QVault TPM based post‑quantum capabilities with Lattice’s long-running leadership in secure, power‑efficient FPGA platforms, we further expand our quantum-capable portfolio of solutions that give our customers a variety of ways to achieve quantum-resilience in their designs with strong assurance and performance,” said Eric Sivertson, Vice President of Security Business at Lattice Semiconductor.
A Proof-of-Concept of the FPGA-TPM solution integrates a Lattice secure FPGA with SEALSQ’s PQC based QS7001and QVault TPM secure Root-of-Trust (RoT). The PoC demonstrates the technical feasibility of embedding TPM-based post-quantum cryptography directly into FPGA architectures and will serve as a foundational reference design for enhanced edge security.
By combining Lattice’s expertise in low power programmable FPGAs and recognized leadership in security with SEALSQ’s specialized post-quantum capabilities, this collaboration demonstrates technical interoperability and supports broader industry efforts toward next-generation quantum-secure hardware.
This initiative aligns with the launch of the Year of Quantum Security 2026 (YQS2026) in Washington, D.C., where stakeholders from government, industry, and academia converged around a shared conclusion: quantum security is no longer theoretical, it is now an infrastructure and governance imperative. Both companies support industry efforts to advance post-quantum standards recommended by organizations such as NIST.
See Live Demonstrations at Embedded World 2026
The new post-quantum security PoC demo will be on display at Embedded World 2026 from March 10-12, 2026 in Nuremberg, Germany. Visit Lattice’s exhibit at Hall 4, Booth #528 to experience the unified FPGA-TPM architecture delivering a trusted root of resilience and crypto updatability at the edge, and hear more from Eric Sivertson during his Embedded World conference on the topic (Trusted Resilience Edge: Unified FPGA-TPM for Post-Quantum Cryptography RED & Cyber Resilience Act) on Tuesday March 10th at 5PM.
