Insider Brief
- SECQAI has successfully taped out its SE01 “Q-Locked” CHERI ISA V9 Trusted Platform Module (TPM) with TSMC on a 22nm process, marking a major milestone for scalable, memory-safe, quantum-secure computation.
- The Q-Locked TPM integrates memory safety via the CHERI ISA v9 and supports NIST-approved post-quantum cryptography (PQC) algorithms, enabling secure hardware-level cryptography for commercial servers, AI infrastructure, and consumer devices.
- The development addresses widespread memory vulnerabilities and positions SECQAI to provide OEMs with future-proof, hardware-accelerated PQC solutions, in collaboration with partners like TSMC and VCA IMEC.
PRESS RELEASE — a leading provider of ultra secure semiconductor solutions, has announced its SE01 “Q-Locked” CHERI ISA V9 TPM was successfully taped out with TSMC on their industry leading 22nm process. This is a significant achievement which marks the scalable commercial availability of memory safe, quantum secure computation at scale for customers from around the world. The SE01 Q-Locked TPM is a key step for SECQAI in its mission of making devices all around the world safer and more secure.
SECQAI has developed its ‘Q-Locked’ range to address the significant number of memory vulnerabilities which enable cyberattacks every day, while providing the hardware capability for customers to deploy Post Quantum Cryptography (PQC) at scale.
The Trusted Platform Module (TPM) is one of the critical security primitives needed to ensure the integrity and authenticity of hardware platforms, whether that be commercial servers, AI infrastructure or consumer laptops. They enable secure cryptographic key generation and storage, the authentication of the device or system (it is what it professes tobe), while also ensuring its own internal integrity (it hasn’t been tampered with). Considered against an ever-evolving threat landscape and increased uncertainty around the world, it’s more important than ever to ensure devices are secured at the lowest level: in hardware.
Secure by design, SECQAI has revolutionised the resilience of the TPM, redesigning it from the ground, up. Its memory safety comes from the commercial-ready implementation of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA v9, as pioneered by the University of Cambridge’s Department of Computer Science and Technology. The Q-Locked TPM has been designed towards FIPS 140-3 standards, enabling the acceleration of critical PQC algorithms, as defined under NIST standards. This is powering the transition for OEMs to PQC
Memory safety at its core
Research by Microsoft has shown that approximately 70% of Common Vulnerabilities and Exposures (CVEs) are related to memory safety issues. By incorporating memory safety into the semiconductors embedded in servers and devices, we can scale this protection across Critical National Infrastructure and our economies more broadly, reducing our attack surface.
The CHERI architecture is based on the RISC-V instruction set architecture (ISA) and extends it with new capability-related instructions, making the designs memory safe. These include new instructions for working with capabilities, including loads, stores, and manipulations.
The development and standardisation of the v9 ISA has been spearheaded by the team at the University of Cambridge and SRI International.
Enabling Post-Quantum Cryptography
The impending threat of quantum computing to classical cryptography highlights the need for post-quantum cryptography (PQC) solutions. By accelerating customer capabilities to run PQC algorithms in hardware, we can ensure that sensitive information remains secure even in the face of advanced computational attacks. SECQAI’s Q-Locked TPM supports NIST approved PQC algorithms (FIPS 203, 204 and 205), providing OEMs with a future-proof solution for secure computing.
“We are thrilled to have achieved this major milestone,” said Rahul Tyagi, CEO of SECQAI. “We have worked closely with our large OEM partners to deliver on the critical need for more secure chips in the market. Our collaboration with TSMC and their VCA IMEC has been instrumental in bringing this innovative solution to market. We look forward to working with the industry to enable widespread adoption of memory safe, secure computation.”
