Insider Brief
- IBM and Siemens are collaborating to advance IBM’s 3D nanostack transistor architecture, focusing on design, simulation, lithography and manufacturing preparation.
- IBM says the current 7-angstrom design uses vertically stacked, staggered nanosheet transistors and could improve chip density, energy efficiency, performance and SRAM scaling.
- The companies will develop virtual models and refine design and fabrication techniques to address manufacturing challenges and prepare future nanostack generations for production.
PRESS RELEASE — Today, IBM (NYSE: IBM), in collaboration with Siemens, announced new research aimed at advancing IBM’s nanostack architecture, a new transistor architecture unveiled by IBM earlier this year. The collaboration will bring together IBM’s leadership in semiconductor device innovation and Siemens’ expertise in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software to accelerate the development of nanostack.
Nanostack is the industry’s first known three-dimensional, nanosheet-based design, vertically stacking and staggering transistors to pack more transistors onto a chip, with nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also unlocks the use of different material combinations within each stacked layer to optimize performance and power efficiency of each transistor independent of the other. These innovations power substantial leaps in energy efficiency, performance, and SRAM scaling.
Earlier this year, IBM demonstrated the viability of the nanostack architecture. Now, additional advances are needed to prepare the technology for manufacturing and production at scale.
Through this collaboration, IBM and Siemens will work to advance the design, simulation, and lithography techniques needed for this and future nanostack generations beyond the current 7 angstrom node. The collaboration includes developing advanced virtual models of nanostack in order to model performance, optimize designs, and address fabrication challenges before chips are built.
“Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade,” said Huiming Bu, Vice President of Silicon Technology R&D, IBM. “We are thrilled to work with Siemens as we continue to advance this technology and explore new approaches to extend angstrom-level scaling with nanostack.”
“Scaling semiconductors into the angstrom era demands tightly coupled co-optimization between device physics, EDA design and manufacturing software, and manufacturing. As physical AI places extraordinary demands on silicon architecture, IBM‘s 3D nanostack design represents a pivotal leap forward,” said Ankur Gupta, Executive Vice President, EDA IC Portfolio, Siemens. “Siemens’ collaboration with IBM to advance virtual modeling, simulation, lithography, and design software optimizations needed to address physical limitations early and accelerate the development of these complex architectures is truly pioneering.”
By combining IBM‘s semiconductor leadership with Siemens’ advanced EDA software and simulation technologies, the companies aim to accelerate technology development cycles and advance the manufacturing foundation necessary for bringing nanostack toward production.
