Insider Brief
- Alice & Bob’s new quantum error correction architecture is designed to reduce hardware requirements for useful quantum computers.
- Researchers report the approach will allow the operation of 100 high-fidelity logical qubits (with an error rate of 10-8) with as little as 1,500 physical cat qubits.
- The findings are available on the pre-print server arXiv.
PRESS RELEASE — Alice & Bob, a leading hardware developer in the race to fault tolerant quantum computers, in collaboration with the research institute Inria, today announced a new quantum error correction architecture – low-density parity-check (LDPC) codes on cat qubits – to reduce hardware requirements for useful quantum computers.
The theoretical work, available on arXiv, advances previous research on LDPC codes by enabling the implementation of gates as well as the use of short-range connectivity on quantum chips.
The resulting reduction in overhead required for quantum error correction will allow the operation of 100 high-fidelity logical qubits (with an error rate of 10-8) with as little as 1,500 physical cat qubits.
“Over 90% of quantum computing value depends on strong error correction, which is currently many years away from meaningful computations,” said Jean-François Bobier, Partner and Director at the Boston Consulting Group. “By improving correction by an order of magnitude, Alice & Bob’s combined innovations could deliver industry-relevant logical qubits on hardware technology that is mature today.”
“This new architecture using LDPC codes and cat qubits could run Shor’s algorithm with less than 100,000 physical qubits, a 200-fold improvement over competing approaches’ 20 million qubit requirement.” said Théau Peronnin, CEO of Alice & Bob. “Our approach makes quantum computers more realistic in terms of time, cost and energy consumption, demonstrating our continued commitment to advancing the path to impactful quantum computing with error corrected, logical qubits.”
Cat qubits alone already enable logical qubit designs that require significantly fewer qubits, thanks to their inherent protection from bit flip errors. In a previous paper by Alice & Bob and CEA, researchers demonstrated how it would be possible to run Shor’s algorithm with 350,000 cat qubits, a 60-fold improvement over the state-of-the art.
LDPC codes are a class of efficient error correction codes that reduce hardware requirements to correct errors occurring in information transfer and storing. By using LDPC codes on a cat-qubit architecture, this latest work not only shows how the qubit footprint of a fault tolerant quantum computer could be further reduced but overcomes two key challenges for the implementation of quantum LDPC (qLDPC) codes.
Alice & Bob recently announced the tape out of a chip that would encode their first logical qubit prototype, known as Helium 1. When logical qubits with a sufficiently low error rate are implemented and using the cat qubit LDPC code technique, Alice & Bob would be capable of harnessing the computing power of 100 logical qubits with as little as 1,500 physical qubits, to run fault-tolerant algorithms.
As leading superconducting quantum computing manufacturers like IBM offer up to 1,121 physical qubits, outperforming classical computers in the simulation of quantum systems (quantum supremacy) is a milestone that would become attainable within current hardware capabilities using Alice & Bob new architecture.
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