SEEQC Combines Chip-Based Processing With NVIDIA AI to Improve Quantum Error Correction

Insider Brief

• SEEQC reported simulation results showing that combining its chip-based pre-decoder with NVIDIA Ising reduced quantum error-correction decoding time and logical error rates by approximately 50% compared with using Ising alone.
• The architecture places specialized processing closer to the quantum processor to reduce data transfers and support faster communication with GPU-based computing systems.
• SEEQC plans to integrate the demonstrated components into a quantum processor connected to high-performance computing infrastructure and evaluate further improvements in error correction and scalability.

PRESS RELEASE — –  SEEQC, Inc. (“SEEQC” or the “Company”),a chip-based quantum computing company, today announced results demonstrating significant performance improvements in quantum error correction decoding through a digital interface optimized multi-stage decoding architecture combining SEEQC’s chip-based pre-decoder technology with the NVIDIA Ising open family of AI models.

SEEQC’s chip-based pre-decoder was integrated in a simulated quantum processor and architecture stack incorporating realistic decoder latency at scale, as a backend to NVIDIA Ising Decoding with SEEQC Digital Link and NVIDIA NVQLink providing the framework for low-latency communication between quantum and GPU-accelerated compute environments. Compared with operating NVIDIA Ising as a standalone pre-decoder, the combined multi-stage pre-decoder architecture demonstrated an approximately 50% reduction in decoding latency and logical error rate performance, the two key metrics that dictate the scalability of a fault tolerant quantum system. The overheads associated with error correction are enormous and can increase exponentially as systems scale towards useful computation. Therefore, a 50% improvement in these key scaling bottleneck metrics have a significant impact on the overall scalability and efficiency of a quantum processor.

The results demonstrate how specialized processing integrated at a chip-scale closer to the QPU complements GPU-accelerated decoding to improve performance of the overall quantum-classical system. By reducing the amount of information transferred to higher-level classical compute resources and accelerating critical decoding functions, the architecture provides a potential path toward faster and more scalable quantum error correction, whilst lowering the overheads and performance requirements of the underlying quantum processor.

“We believe the future of quantum computing will be enabled by the tightest possible integration of quantum processors with advanced high-performance computing infrastructure,” said John Levy, Chief Executive Officer of SEEQC. “These results demonstrate the role SEEQC’s digital chip technology can play at that critical interface. Bringing specialized processing closer to the qubits while connecting efficiently to GPU-accelerated computing provides a pathway toward quantum systems that can operate at significantly greater scale.”

“Open models like Ising and open interfaces like NVQLink enable quantum builders to accelerate their own hardware advances with AI and GPU computing,” said Sam Stanwyck, director of quantum product at NVIDIA. “SEEQC’s work with NVIDIA Ising Decoding and NVQLink shows how that approach can deliver results, with its chip-based pre-decoder helping achieve faster decoding and fewer logical errors.”

“Quantum error correction is fundamentally a systems challenge, where latency, data movement and logical error performance all become increasingly critical as quantum processors scale,” said Matt Hutchings, Chief Product Officer of SEEQC. “By combining SEEQC’s digital pre-decoder architecture and Digital Link with NVQLink and the NVIDIA Ising  pre-decoder, we demonstrated how a tightly integrated, multi-stage decoding architecture can materially improve key performance metrics. This is the type of architecture we believe will be required to make fault-tolerant quantum computing practical at scale.”

The results build on an ongoing collaboration focused on integrating quantum processors with GPUaccelerated computing infrastructure. SEEQC has been developing methods to combine its digital quantum computing architecture with NVIDIA’s quantum platform to address critical challenges in scalable quantum systems. The next step is to integrate the system level components demonstrated to date to enable chip-to-chip integration of a quantum processor within an advanced HPC infrastructure delivering the performance and scalability required to unlock applications in quantum AI.

This work will enable SEEQC to evaluate additional opportunities to improve the performance and scalability of quantum error correction and other hybrid quantum-classical workloads.